# Build 2 bits Serial Adder

### What inputs and outputs does it have?

The serial adder system efficiently handles two input bits, X1 and X2, to compute the sum and carry. This system guarantees accuracy with two separate outputs: S for sum and C for carry, all synchronized smoothly by a single clock. The input sequence begins with the least significant bit (LSB) and progresses to the most significant bit (MSB), updating the serial bits at each rising clock edge

### How it does behave?

The serial adder system needs to include a memorization step to ensure efficiency. While calculating the sum is simple, a memory component is necessary to determine the carry. The chosen method entails using a D flip-flop as a memorization cell, synchronized with the data clock signal. The system will operate in two distinct states: State A with no carry (C=0) and State B with a carry (C=1).

Notice that X1 will be green colored, X2 blue colored, and the output S will be red

### Stat diagram

### Stat Table

Present Position | X1 X2 = 00 | X1 X2 = 01 | X1 X2 = 10 | X1 X2 = 11 | ||||

Next Stat | Output | Next Stat | Output | Next Stat | Output | Next Stat | Output | |

A | A | 0 | A | 1 | A | 1 | B | 0 |

B | A | 1 | B | 0 | B | 0 | B | 1 |

### Excitation Table

Present state | X1 | X2 | Next Step | D flip-flop | Output |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 0 | 1 |

0 | 1 | 0 | 0 | 0 | 1 |

0 | 1 | 1 | 1 | 1 | 0 |

1 | 0 | 0 | 0 | 0 | 1 |

1 | 0 | 1 | 1 | 1 | 0 |

1 | 1 | 0 | 1 | 1 | 0 |

1 | 1 | 1 | 1 | 1 | 1 |

### D K-map table

Next step NS | X1 X2=00 | X1 X2=01 | X1 X2=11 | X1 X2=10 |

0 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 1 | 1 |

D=NS.X1 +NS.X2 + X1.X2 |

### Carry K-map table

Next step NS | X1 X2=00 | X1 X2=01 | X1 X2=11 | X1 X2=10 |

0 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 1 | 0 |

D=X1 ΘX2 Θ NS |